[coreboot-gerrit] [M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...

[Tim Van Patten (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Chris Wang, Martin Roth, Fred Reitberger, Felix Held.

Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )

Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
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Patch Set 31:

(1 comment)

File src/soc/amd/mendocino/root_complex.c:

https://review.coreboot.org/c/coreboot/+/68649/comment/2098ae39_e2548f75 
PS16, Line 393: #else
> since the below settings will apply to dptc parameters, it's better to follow AMD IRM, or you have your own setting that needs to apply to.

I don't fully understand what this means. What is "AMD IRM"?

However, regarding:
> There's no other STT setting that will be changed via DPTC, so those values will keep the value you set to default in devtree.

My point is that the values added to `DPTC_INPUTS()` are **not** defined in the device tree for all other Mendocino boards. Only `winterhold/overridetree.cb` has the values defined, so they need to be added to `baseboard/devicetree.cb` (once https://review.coreboot.org/c/coreboot/+/69904 lands), so every Mendocino board has valid values.