[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/common/block/lpc: Limit ROM2 to 16MiB

[Patrick Rudolph (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86582?usp=email )

Change subject: soc/amd/common/block/lpc: Limit ROM2 to 16MiB
......................................................................

soc/amd/common/block/lpc: Limit ROM2 to 16MiB

Don't map more than 16MiB when the SPI ROM size is bigger than 16MiB.

Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89
Signed-off-by: Patrick Rudolph 
---
M src/soc/amd/common/block/lpc/lpc_util.c
1 file changed, 4 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/86582/1

diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 309825a..6e4ddcb 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -277,8 +277,11 @@
     * 0xffe0(0000): 2MB
     * 0xffc0(0000): 4MB
     */
-	pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
+	if (CONFIG_COREBOOT_ROMSIZE_KB <= 16384)
+		pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
    				- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+	else
+		pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0xff00);

/* Enable LPC ROM range end at 0xffff(ffff). */
    pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);