Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50292 )
Change subject: soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option ......................................................................
soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option
No board in tree selects a different base address, so this can be removed from Kconfig and be treated like the other base addresses in the I/O space that are defines in iomap.h.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Iec3d4476e3a6a5d2b226edef4c41f503a0c81f33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50292 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/include/soc/iomap.h 2 files changed, 1 insertion(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index baf3f4e..b400e1b 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -250,13 +250,6 @@ Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode.
-config STONEYRIDGE_ACPI_IO_BASE - hex - default 0x400 - help - Base address for the ACPI registers. - This value must match the hardcoded value of AGESA. - config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL hex diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 92d99e4..d8befbe 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -27,7 +27,7 @@
/* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 -#define ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE +#define ACPI_IO_BASE 0x400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */