Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42838 )
Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ......................................................................
soc/amd/picasso/soc_util: add comment on the silicon and soc types
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/soc_util.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/42838/1
diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 8a1f8ef..887a71b 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -9,6 +9,14 @@ #include <soc/soc_util.h> #include <types.h>
+/* + * The Zen/Zen+ based APUs can be RV (sometimes called RV1), PCO or RV2 silicon. RV2 has less + * PCIe, USB3 and Displayport connectivity than RV(1) or PCO. A Picasso SoC is always PCO + * silicon, a Dali SoC can either be RV2 or fused-down PCO silicon that has the same + * connectivity as the RV2 one and Pollock is always RV2 silicon. Picasso and Dali are in a FP5 + * package while Pollock is in the smaller FT5 package. + */ + #define SOCKET_TYPE_SHIFT 28 #define SOCKET_TYPSE_MASK (0xf << SOCKET_TYPE_SHIFT)