[coreboot-gerrit] [S] Change in coreboot[master]: [Code Migration] Boot time cache information prints

[Dinesh Gehlot (Code Review)]

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69615 )

Change subject: [Code Migration] Boot time cache information prints
......................................................................

[Code Migration] Boot time cache information prints

Signed-off-by: Dinesh Gehlot 
Change-Id: Ic7039a44f5f6ca0f9771bcc701f6cd21ca70ee9f
---
M src/soc/intel/meteorlake/bootblock/report_platform.c
1 file changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/69615/1

diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c
index 63f1771..510e3b7 100644
--- a/src/soc/intel/meteorlake/bootblock/report_platform.c
+++ b/src/soc/intel/meteorlake/bootblock/report_platform.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <commonlib/helpers.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/cpu_ids.h>
@@ -64,6 +65,21 @@
    return pci_read_config16(dev, PCI_DEVICE_ID);
 }

+static void report_cache_info(void)
+{
+	int cache_level = CACHE_L3;
+	struct cpu_cache_info info;
+
+	if (!fill_cpu_cache_info(cache_level, &info))
+		return;
+
+	printk(BIOS_INFO, "Cache: Level %d: ", cache_level);
+	printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n",
+		info.num_ways, info.physical_partitions, info.line_size, info.num_sets);
+
+	printk(BIOS_INFO, "Cache size = %zu MiB\n", get_cache_size(&info)/MiB);
+}
+
 static void report_cpu_info(void)
 {
    u32 i, cpu_id, cpu_feature_flag;
@@ -94,6 +110,8 @@
    printk(BIOS_DEBUG,
    	"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
    	mode[aes], mode[txt], mode[vt]);
+
+	report_cache_info();
 }

static void report_mch_info(void)