Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/27240
Change subject: google/grunt: revert "stoneyridge: Move agesa out of bootblock" ......................................................................
google/grunt: revert "stoneyridge: Move agesa out of bootblock"
with CL:26478, test FAFT firmware_CorruptFwSigB on Grunt/Careena will cause BIOS FW crash and it can only recover by re-flash BIOS.
so reverts CL:26478 to fix FAFT firmware_CorruptFwSigB test fail.
BUG=none BRANCH=master TEST=emerge-grunt coreboot run FAFT firmware_CorruptFwSigB and pass Change-Id: I6e30e3a5625f83778c9a217d79b8fef36736c5a1 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/romstage.c 2 files changed, 57 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/27240/1
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 7b2c420..d431c43 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -73,6 +73,27 @@ CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); }
+/* + * To move AGESA calls to romstage, just move agesa_call() and bsp_agesa_call() + * to romstage.c. Also move the call to bsp_agesa_call() to the marked location + * in romstage.c. + */ +static void agesa_call(void) +{ + post_code(0x37); + do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); + + post_code(0x38); + /* APs will not exit amdinitearly */ + do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); +} + +static void bsp_agesa_call(void) +{ + set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ + agesa_call(); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { amd_initmmio(); @@ -97,6 +118,37 @@ post_code(0x90); }
+/* + * This step is in bootblock because the SMU FW1 must be loaded prior to + * issuing any reset to the system. Set up just enough to get the command + * to the PSP. A side effect of placing this step here is we will always + * load a RO version of FW1 and never a RW version. + * + * todo: If AMD develops a more robust methodology, move this function to + * romstage. + */ +static void load_smu_fw1(void) +{ + u32 base, limit, cmd; + + /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ + base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; + limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); + + /* Preload a value into "BAR3" and enable it */ + pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); + pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); + + /* Enable memory access and master */ + cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); + + psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); +} + void bootblock_soc_init(void) { if (IS_ENABLED(CONFIG_STONEYRIDGE_UART)) @@ -106,6 +158,11 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+ if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) + load_smu_fw1(); + + bsp_agesa_call(); + /* Initialize any early i2c buses. */ i2c_soc_early_init(); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 78472d3..a742cd0 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -41,44 +41,6 @@ /* By default, don't do anything */ }
-static void load_smu_fw1(void) -{ - u32 base, limit, cmd; - - /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ - base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); - - /* Preload a value into "BAR3" and enable it */ - pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); - pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); - - /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); -} - -static void agesa_call(void) -{ - post_code(0x37); - do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); - - post_code(0x38); - /* APs will not exit amdinitearly */ - do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); -} - -static void bsp_agesa_call(void) -{ - set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ - agesa_call(); -} - asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -99,12 +61,6 @@
console_init();
- if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) - load_smu_fw1(); - - - bsp_agesa_call(); - mainboard_romstage_entry(s3_resume);
if (!s3_resume) {