[coreboot-gerrit] Change in coreboot[master]: nb/intel/ironlake: Drop unnecessary `smm_region_start` function

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45919 )

Change subject: nb/intel/ironlake: Drop unnecessary `smm_region_start` function
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nb/intel/ironlake: Drop unnecessary `smm_region_start` function

Change-Id: I4c4b40b2b4f54b7756b8485dad80a1b4786270f7
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45919
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/northbridge/intel/ironlake/memmap.c
1 file changed, 3 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c
index 54337cc..78fbae8 100644
--- a/src/northbridge/intel/ironlake/memmap.c
+++ b/src/northbridge/intel/ironlake/memmap.c
@@ -11,16 +11,10 @@

#include "ironlake.h"

-static uintptr_t smm_region_start(void)
-{
-	/* Base of TSEG is top of usable DRAM */
-	uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
-	return tom;
-}
-
 static uintptr_t northbridge_get_tseg_base(void)
 {
-	return smm_region_start();
+	/* Base of TSEG is top of usable DRAM */
+	return pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
 }

static size_t northbridge_get_tseg_size(void)
@@ -30,7 +24,7 @@

void *cbmem_top_chipset(void)
 {
-	return (void *) smm_region_start();
+	return (void *)northbridge_get_tseg_base();
 }

void smm_region(uintptr_t *start, size_t *size)