Attention is currently required from: Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Eugene Myers has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55621 )
Change subject: soc/intel: Add get_pmbase ......................................................................
soc/intel: Add get_pmbase
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access.
Original-Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Original-Signed-off-by: Eugene D. Myers edmyers@tycho.nsa.gov Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990 Original-Reviewed-by: Patrick Georgi pgeorgi@google.com Original-Tested-by: build bot (Jenkins) no-reply@coreboot.org
Change-Id: I7f9ef32946a17aa0bbcbc375bc34b48e62620694 Signed-off-by: Eugene Myers edmyers@tycho.nsa.gov --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pmutil.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c A src/soc/intel/fsp_broadwell_de/include/soc/pm.h M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c 15 files changed, 91 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/55621/1
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d0b0421..22e414c 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -250,4 +250,7 @@
void enable_pm_timer_emulation(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 559adad..8151afc 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -246,3 +246,9 @@
return rtc_failure; } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 18004fa..c9074d8 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -155,4 +155,7 @@ /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 00db615..2445dfa 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -458,3 +458,9 @@
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 5b85e74..356f0bc 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -172,5 +172,8 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 428a89f..5774873 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -273,3 +273,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pm.h b/src/soc/intel/fsp_broadwell_de/include/soc/pm.h new file mode 100644 index 0000000..c1b6ee9 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pm.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2016-2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_FSP_BROADWELL_DE_PM_H_ +#define _SOC_FSP_BROADWELL_DE_PM_H_ + +/* + * Brings in get_pmbase so that StmPlatformResource.c can build + * under 4.11 + */ + +#include <soc/acpi.h> +#endif diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 44888ec..34c32a9 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -171,5 +171,8 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 8efd426..a4971da 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -272,3 +272,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index ffcd91f..5006b19 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -104,3 +104,10 @@ printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl);
} + +uint16_t get_pmbase(void) +{ + struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; +} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index a3fb02f..e02b8a2 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -27,4 +27,7 @@ struct chipset_power_state *get_power_state(void); int fill_power_state(void);
+/* STM Support */ +uint16_t get_pmbase(void); + #endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 18b0c15..007d29c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -197,4 +197,7 @@ return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); }
+/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 329cea9..aac5d1d 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -266,3 +266,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index fb9b67b..d2f47e2 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -177,5 +177,7 @@ /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void);
+/* STM Support */ +uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 53f8609..39659c3 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -274,3 +274,9 @@ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +}