Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )
Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... PS2, Line 1599: 796 I wonder if it'll be more clear if we do
const clock_rate_delta = 4; /* 4MHz to reduce interference from RF peripherals like modem, WiFi, Bluetooth */
switch (freq_group) { case LP4X_DDR1600: clock_rate = 1600 / 2 - clock_rate_delta; break;
case LP4X_DDR2400: clock_rate = 2400 / 2 - clock_rate_delta;
...