[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Enable cache in bootblock

[Raul Rangel (Code Review)]

Raul Rangel has uploaded a new patch set (#10) to the change originally created by Marshall Dawson. ( https://review.coreboot.org/c/coreboot/+/38691 )

Change subject: soc/amd/picasso: Enable cache in bootblock
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soc/amd/picasso: Enable cache in bootblock

Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM
setup code to properly enable MTRRs.  Add that capability to the
bootblock_c_entry() function.  In addition, enable an MTRR to cache
(WP) the flash boot device and another for WB of the non-XIP bootblock
running in DRAM.

BUG=b:147042464
TEST=Boot trembyle to payload and make sure bootblock isn't abnormally
slow.

Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/bootblock/bootblock.c
1 file changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38691/10