Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )
Change subject: arch/x86: Cache the TSEG region at the top of ram ......................................................................
Patch Set 4:
I like the idea of adding smm region as WB to the postar mtrr solution. A common API for doing that is helpful . To do it automatically we can add a Kconfig and do this conditional call in run_postcar_phase() or just make the appropriate call in the appropriate romstage.c file.
CB:34897
I think platform only has to provide an upper boundary for WB which is not allowed to move upwards and a lower boundary (cbmem_top() - 16*MiB) that common code is allowed to move downwards if it results with lesser use of MTRRs. Are there any cases where we would need UC hole there in the middle?