Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35537 )
Change subject: sb/intel/spi: Use different SPIOPS for most SST flashes ......................................................................
Patch Set 4: Code-Review+2
(4 comments)
https://review.coreboot.org/c/coreboot/+/35537/2/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/35537/2/src/southbridge/intel/commo... PS2, Line 1056: : const char *(aai_write_flash[]) = { : "SST25VF040B", : "SST25VF080B", : "SST25VF080", : "SST25VF016B", : "SST25VF032B", : "SST25WF512", : "SST25WF010", : "SST25WF020", : "SST25WF040", : "SST25WF080", : "SST25WF080B" : };
flashchips.c also mentions a lot that use 0xaf (and don't support 0xad I guess). […]
Ack
https://review.coreboot.org/c/coreboot/+/35537/2/src/southbridge/intel/commo... PS2, Line 1102: const struct spi_flash *flash = boot_device_spi_flash();
can it return NULL?
Done
https://review.coreboot.org/c/coreboot/+/35537/3/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/35537/3/src/southbridge/intel/commo... PS3, Line 1098: ==
wups
Done
https://review.coreboot.org/c/coreboot/+/35537/4/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/35537/4/src/southbridge/intel/commo... PS4, Line 1078: {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ : {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ : {0x03, READ_WITH_ADDR}, /* READ: Read Data */ : {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ : {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ : {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ : {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */ : {0x04, WRITE_NO_ADDR} /* Write Disable */ Maybe align the comments like above?