[coreboot-gerrit] [S] Change in coreboot[main]: soc/amd/common/block/pci: Ignore disabled bridges

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86216?usp=email )

Change subject: soc/amd/common/block/pci: Ignore disabled bridges
......................................................................

soc/amd/common/block/pci: Ignore disabled bridges

To avoid PCI resource conflicts always assert and ignore when
an internal dummy PCIe bridge is marked as disabled. This allows to
boot on AMD/birman+ to UEFI shell.

The PCI bridge device will get properly configured and as the
scan for sub-ordinate devices is disabled, will not delay boot and
will never claim any resources.

Change-Id: Ia97098c860aa6cd6b0b59aa7b1c6f7c239e41983
Signed-off-by: Patrick Rudolph 
---
M src/soc/amd/common/block/pci/pcie_gpp.c
1 file changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/86216/1

diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c
index 0f983d0..9cc4c45 100644
--- a/src/soc/amd/common/block/pci/pcie_gpp.c
+++ b/src/soc/amd/common/block/pci/pcie_gpp.c
@@ -47,6 +47,28 @@
    acpigen_pop_len(); /* Scope */
 }

+struct device_operations amd_pcie_disabled_gpp_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.acpi_name		= pcie_gpp_acpi_name,
+	.acpi_fill_ssdt		= acpi_device_write_gpp_pci_dev,
+};
+
+static void pcie_internal_gpp_enable(struct device *dev)
+{
+	assert(dev->enabled);
+	if (!dev->enabled) {
+		/*
+		 * Cannot hide PPB devices! Must keep them enabled to
+		 * make sure PCI enumeration runs and avoids resource conflicts.
+		 */
+		dev->enabled = true;
+		dev->hidden = true;
+		dev->ops = &amd_pcie_disabled_gpp_ops;
+	}
+}
+
 /* Latency tolerance reporting, max snoop/non-snoop latency value 1.049ms */
 #define PCIE_LTR_MAX_LATENCY_1049US 0x1001

@@ -62,6 +84,7 @@
 };

struct device_operations amd_internal_pcie_gpp_ops = {
+	.enable			= pcie_internal_gpp_enable,
    .read_resources		= pci_bus_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_bus_enable_resources,