[coreboot-gerrit] [S] Change in coreboot[master]: nb/intel/gm45: Make polling loops more explicit

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69077 )

Change subject: nb/intel/gm45: Make polling loops more explicit
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nb/intel/gm45: Make polling loops more explicit

Replace `while (...);` with `do {} while (...);` so that it's easier to
distinguish polling loops from something else, like function calls. The
`{}` can be understood as "nothing", so that the construct is naturally
read as "do nothing while (...)".

Another reason to prefer this method is that Jenkins does not complain.

Change-Id: Ifbf3cf072f8b817b2fdeece4ef89bae0822bb6e6
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69077
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
Reviewed-by: Felix Held 
---
M src/northbridge/intel/gm45/pcie.c
1 file changed, 24 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Arthur Heymans: Looks good to me, but someone else must approve

diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 295bf5b..59a4992 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -33,12 +33,12 @@
    epbar_write32(EP_PORTARB(7), 0x00005555);
    epbar_setbits32(EPVC1RCTL, 1 << 16);

-	while ((epbar_read8(EPVC1RSTS) & 1) != 0);
+	do {} while ((epbar_read8(EPVC1RSTS) & 1) != 0);

/* VC1: enable */
    epbar_setbits32(EPVC1RCTL, 1 << 31);

-	while ((epbar_read8(EPVC1RSTS) & 2) != 0);
+	do {} while ((epbar_read8(EPVC1RSTS) & 2) != 0);
 }

/* MCH side */
@@ -56,7 +56,7 @@
    /* VC1: enable */
    dmibar_setbits32(DMIVC1RCTL, 1 << 31);

-	while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);
+	do {} while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);

/* additional configuration. */
    dmibar_setbits32(0x200, 3 << 13);