[coreboot-gerrit] Change in coreboot[master]: soc/intel{cnl,icl,skl,tgl}\bootblock: Make sure DMI PCR 2770 is set

[Wim Vervoorn (Code Review)]

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38746 )

Change subject: soc/intel{cnl,icl,skl,tgl}\bootblock: Make sure DMI PCR 2770 is set
......................................................................

soc/intel{cnl,icl,skl,tgl}\bootblock: Make sure DMI PCR 2770 is set

DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI
offset 0x80. This is specified in PCH BWG par 2.5.1.5.

Add the support to make sure this PCR is always set correctly.

BUG=N/A
TEST=tested on facebook monolith.

Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d
Signed-off-by: Wim Vervoorn 
---
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/tigerlake/bootblock/pch.c
4 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38746/1

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index a6e9f9d..e7b79a0 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -172,6 +172,11 @@
    	 * value program in LPC PCI offset 82h.
    	 */
    	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+		/*
+		 * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+		 * value programmed in LPC PCI offset 80h.
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
    }

/* Program generic IO Decode Range */
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index fd2ffd2..b1309a4 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -144,6 +144,11 @@
    	 * value program in ESPI PCI offset 82h.
    	 */
    	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+		/*
+		 * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+		 * value programmed in LPC PCI offset 80h.
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
    }

/* Program generic IO Decode Range */
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index ddf1139..7763cf0 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -140,6 +140,12 @@
    	 * value program in LPC PCI offset 82h.
    	 */
    	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+		/*
+		 * As per PCH BWG 2.5.1.5.
+		 * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+		 * value programmed in LPC PCI offset 80h.
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
    }

/* Program generic IO Decode Range */
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 1654809..8a132ce 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -169,6 +169,11 @@
    	 * value program in ESPI PCI offset 82h.
    	 */
    	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+		/*
+		 * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+		 * value programmed in LPC PCI offset 80h.
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
    }

/* Program generic IO Decode Range */