[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add SMRR Locking support

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Subrata Banik, Kane Chen, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45013

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake: Add SMRR Locking support
......................................................................

soc/intel/tigerlake: Add SMRR Locking support

The SMRR MSRs can be locked, so that a further write to them will cause
a #GP.  This patch adds that functionality, but since the MSR is a
core-level register, it must only be done once per core; if the SoC has
hyperthreading enabled, then attempting to write the SMRR Lock bit on
the primary thread will cause a #GP when the secondary (sibling) thread
attempts to also write to this MSR.

BUG=b:164489598
TEST=Boot into OS, verify using `iotools rdmsr` that all threads have
the Lock bit set.

Signed-off-by: Tim Wawrzynczak 
Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/smmrelocate.c
2 files changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45013/5