[coreboot-gerrit] [L] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00

[Subrata Banik (Code Review)]

Attention is currently required from: Alok Agarwal, Bora Guvendik, Jérémy Compostella, Ronak Kanabar, Vikrant L Jadeja.

Subrata Banik has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/85149?usp=email )

Change subject: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
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Patch Set 7:

(1 comment)

File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h:

https://review.coreboot.org/c/coreboot/+/85149/comment/4773857e_af428319?usp... :
PS7, Line 2387: 
              : /** Offset 0x0976 - VR Fast Vmode ICC Limit support
              :   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
              :   to feature disabled (no reactive protection). This value represents the current
              :   threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
              :   The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for
              :   GT, [2] for SA, [3] through [5] are Reserved.
              : **/
              :   UINT16                      IccLimit[6];
this is hand edited header file IMO because after creating the FSP partial header for FSP 2431.00, I don't see this UPD existed inside FSP partial header