Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82090?usp=email )
(
10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Move VPD based settings to mainboard codes ......................................................................
soc/intel/xeon_sp: Move VPD based settings to mainboard codes
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes.
This patch moves the VPD based settings (FSP log level, et al) from SoC codes to mainboard codes.
TEST=Build and boot on intel/archercity CRB with no significant log differences
Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91 Signed-off-by: Shuo Liu shuo.liu@intel.com Signed-off-by: Jincheng Li jincheng.li@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090 Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/archercity_crb/romstage.c M src/mainboard/inventec/transformers/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 3 files changed, 33 insertions(+), 85 deletions(-)
Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved
diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c index 6e4bd8e..ff56f59 100644 --- a/src/mainboard/intel/archercity_crb/romstage.c +++ b/src/mainboard/intel/archercity_crb/romstage.c @@ -35,17 +35,23 @@
void mainboard_memory_init_params(FSPM_UPD *mupd) { - uint8_t val; - - /* Send FSP log message to SOL */ - if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n", - FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + /* Setup FSP log */ + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } }
+ /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); + /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; /* Enable - Portions of memory reference code will be skipped diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c index 9299c7d..1abcf70 100644 --- a/src/mainboard/inventec/transformers/romstage.c +++ b/src/mainboard/inventec/transformers/romstage.c @@ -98,22 +98,28 @@
void mainboard_memory_init_params(FSPM_UPD *mupd) { - uint8_t val; - /* Since it's the first IPMI command, it's better to run get BMC selftest result first */ if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { init_frb2_wdt(); }
- /* Send FSP log message to SOL */ - if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + /* Setup FSP log */ + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } }
+ /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); + /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; /* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on warm boots */ diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 39f46ff..bdb9886 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -34,71 +34,8 @@ /* Default weak implementation */ }
-/* - * Search from VPD_RW first then VPD_RO for UPD config variables, - * overwrites them from VPD if it's found. - */ -static void config_upd_from_vpd(FSPM_UPD *mupd) +static void config_upd(FSPM_UPD *mupd) { - uint8_t val; - int val_int; - - /* Send FSP log message to SOL */ - if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to %d\n", - FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; - } - - if (mupd->FspmConfig.SerialIoUartDebugEnable) { - /* FSP memory debug log level */ - if (vpd_get_int(FSP_MEM_LOG_LEVEL, VPD_RW_THEN_RO, &val_int)) { - if (val_int < 0 || val_int > 4) { - printk(BIOS_DEBUG, - "Invalid serialDebugMsgLvl value from VPD: " - "%d\n", - val_int); - val_int = FSP_MEM_LOG_LEVEL_DEFAULT; - } - printk(BIOS_DEBUG, "Setting serialDebugMsgLvl to %d\n", val_int); - mupd->FspmConfig.serialDebugMsgLvl = (uint8_t)val_int; - } else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "DebugPrintLevel to %d\n", - FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT); - mupd->FspmConfig.serialDebugMsgLvl = FSP_MEM_LOG_LEVEL_DEFAULT; - } - /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ - if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { - printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); - mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; - } - } - - /* FSP Dfx PMIC Secure mode */ - if (vpd_get_int(FSP_PMIC_SECURE_MODE, VPD_RW_THEN_RO, &val_int)) { - if (val_int < 0 || val_int > 2) { - printk(BIOS_DEBUG, - "Invalid PMIC secure mode value from VPD: " - "%d\n", - val_int); - val_int = FSP_PMIC_SECURE_MODE_DEFAULT; - } - printk(BIOS_DEBUG, "Setting PMIC secure mode to %d\n", val_int); - mupd->FspmConfig.DfxPmicSecureMode = (uint8_t)val_int; - } else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "PMIC secure mode to %d\n", - FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT); - mupd->FspmConfig.DfxPmicSecureMode = FSP_PMIC_SECURE_MODE_DEFAULT; - } - int cxl_mode = get_cxl_mode(); if (cxl_mode == XEONSP_CXL_SYS_MEM || cxl_mode == XEONSP_CXL_SP_MEM) mupd->FspmConfig.DfxCxlType3LegacyEn = 1; @@ -274,9 +211,8 @@ printk(BIOS_DEBUG, "CPU is D stepping, setting package C state to C0/C1\n"); mupd->FspmConfig.CpuPmPackageCState = 0; } - /* Set some common UPDs from VPD, mainboard can still override them if needed */ - if (CONFIG(VPD)) - config_upd_from_vpd(mupd); + + config_upd(mupd); initialize_iio_upd(mupd); mainboard_memory_init_params(mupd);