[coreboot-gerrit] Change in coreboot[master]: [RFC] AMD APM_CNT and SMI enablement

[Felix Held (Code Review)]

Attention is currently required from: Marshall Dawson, Kyösti Mälkki.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42563 )

Change subject: [RFC] AMD APM_CNT and SMI enablement
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Patch Set 1:

(1 comment)

File src/soc/amd/picasso/southbridge.c:

https://review.coreboot.org/c/coreboot/+/42563/comment/77890bbd_d6a3ab7d 
PS1, Line 244: 	pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
> from a quick look i'd say that it's not a bug, since the mmio mapping is used there and not the lega […]

the accesses in romstage to the pm1 and gpe0 registers is via the mmio mapping in the acpimmio region and not via the legacy io mappings that get configured in ramstage. the acpimmio region gets configured early in bootblock (enable_acpimmio_decode_pm04() in fch_pre_init). so this is correct. as far as i've seen the legacy io access is mostly needed for/used in the fadt