Krzysztof M Sywula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32026 )
Change subject: soc/intel/cannonlake: FSP UPD update ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... PS1, Line 169: PchPmSlpS0VmRuntimeControl
I agree with Furquan and I don't believe that's debug/validation thing.
Unless we have hardware/electrical engineer say otherwise, I'm gonna go with what google offers:
"Margining is a test procedure that determines the "safety margin." A parameter is varied to determine the device's sensitivity or ability to perform given a range of inputs. A large number of parts can be characterized to determine a safe range for the specification, to guarantee performance and yield."
or
"Voltage margining is a means of verifying the robustness of a product by intentionally adjusting its supply voltages to their limits and then evaluating the product's performance to ensure that it still meets its specifications at the power supply's extremes."
Again, I don't believe that end customer (person who obtains fully finished device) would ever want voltage margining enabled. S0ix should not be tied in any way to voltage margining. Voltage margining should only be accessible to engineers working on a product.