[coreboot-gerrit] [L] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Shuo Liu, Tim Chu, Tim Wawrzynczak.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email )

Change subject: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain
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Patch Set 7:

(4 comments)

File src/acpi/acpigen_pci.c:

https://review.coreboot.org/c/coreboot/+/81375/comment/0d88aeb6_c2aeca88 :
PS6, Line 217: soc_acpigen_OSC_handle_pcie_request
drop this line

File src/acpi/acpigen_pci.c:

https://review.coreboot.org/c/coreboot/+/81375/comment/c8862589_ecaa3a8d :
PS7, Line 175: acpigen_write_if_lequal_op_int
In between the Arg1 "revision check" and Arg2 "number of arguments" check is missing compared to the DSDT. Without those checks using Local0 as branch hit indicator doesn't make much sense.

https://review.coreboot.org/c/coreboot/+/81375/comment/332d50f4_2074acdc :
PS7, Line 177: LOCAL1_OP
Since RETE is always 0 here, Local1 is always 0.
Thus there's no need to OR something, just write OSC_RET_UNRECOGNIZED_UUID into RETE

File src/include/acpi/acpigen_pci.h:

https://review.coreboot.org/c/coreboot/+/81375/comment/d5a54069_298e28a2 :
PS7, Line 27: soc_acpigen_write_OSC_pci_domain
function prototype should start with `acpigen_` since this code reside in `src/acpi/`