[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
PS5, Line 177: 	enable_ramstage_caching(top_of_ram, top_of_ram_size);
> > > Maybe add a function like postcar_frame_add_romcache() but for both setting up the postcar frame  […]

Also refer to this https://github.com/coreboot/coreboot/blob/ca38fbcdbfcb5024496d2577f71de06745...

TSEG and top_of_ram might not pointed to same MMIO address based on other memory reservation (DMAPR, PRM, ME stolen, PTT etc)