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Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email )
Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ......................................................................
Patch Set 7:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81212/comment/b14dbce7_d8f1735c : PS6, Line 42: 2 MB
i have worked on an Intel project where the CAR size is 1.25MB even. […]
The goal is not to offer a one configuration fit all solution. Each project/board is free to use this feature as it fits the project. Also, SoC variants of a generation have a minimal cache size which we could rely on if it came to a point we wanted it to be the default of a soc configuration.
But I don't believe it is going to make it to the default of a SoC configuration soon. I see it more like an option for a board where SPINOR constraints would be tight and without going through the burden of having to define a fixed `FSP_M_ADDR` and account for it.
Patchset:
PS3:
I'm a bit confused how this works. FSP-M needs to be relocated at runtime for this to work. […]
Done
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/81212/comment/851c3a81_60ff8e5f : PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE
I went with a warning instead of an error to align with other control performed during the compilati […]
@arthur, Let me know what think of the latest "implementation".
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/81212/comment/3ebd6fc2_4e9e6923 : PS6, Line 221: config FSP_M_EXECUTE_FROM_CBFS_CACHE
I realized that PRERAM_CBFS_CACHE is a must item in car now, if there is an Kconfig like USE_PRERAM_ […]
Pre-memory CBFS cache is always on. Only the size can be adjusted with zero meaning no CBFS cache. The Makefile warning if the size is not enough to accommodate the decompressed FSP-M take care of making sure the dependency is satisfied.
https://review.coreboot.org/c/coreboot/+/81212/comment/d2bbe09a_ecd5a03f : PS6, Line 225: Select this value when FSP-M executes from CBFS cache.
i guess the assumptions are not drafted properly about how much temp memory is required to support t […]
Done
https://review.coreboot.org/c/coreboot/+/81212/comment/bd0a33b4_bdde2528 : PS6, Line 225: Select this value when FSP-M executes from CBFS cache.
Maybe we can comment here, if FSP-M is compressed, it will be decompressed into PRERAM_CBFS_CACHE, […]
I also they are technically separated notions even but I added a note about as the whole idea of running from CBFS cache is to have a compressed FSP-M in SPINOR.