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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49136
to look at the new patch set (#5).
Change subject: soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs ......................................................................
soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
List of changes: 1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per EDS. 2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards. 3. Rename PcieRpEnable to PchPcieRpEnable. 4. Enable PEG10 and CPU SSD2 slot(PEG62) in mainboard devicetree.cb.
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 41 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/49136/5