Saurabh Satija (saurabh.satija@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15501
-gerrit
commit 0af885c8ea94aaa56c90d4b21d66be4804a43f94 Author: Saurabh Satija saurabh.satija@intel.com Date: Tue Jun 28 20:33:44 2016 -0700
soc/intel/apollalake: Make global_nvs_t a user defined type
In order to use nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() defined in soc/intel/common/ nhlt.c. These functions are common for all Intel SoCs and use global_nvs_t as a user-defined type.
Change-Id: I4016cdc6a873d26f9fca243084c66e69e0e66a74 Signed-off-by: Saurabh Satija saurabh.satija@intel.com --- src/soc/intel/apollolake/include/soc/nvs.h | 4 ++-- src/soc/intel/common/nhlt.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 3e4f432..bff949e 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -26,7 +26,7 @@
#include <vendorcode/google/chromeos/gnvs.h>
-struct global_nvs_t { +typedef struct global_nvs_t { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ uint8_t ppcm; /* 0x01 - Max PPC State */ @@ -42,6 +42,6 @@ struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -} __attribute__((packed)); +} __attribute__((packed)) global_nvs_t;
#endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index d498152..0ee9424 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -16,6 +16,7 @@ #include <cbmem.h> #include <nhlt.h> #include <soc/acpi.h> +#include <soc/nvs.h>
uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) {