[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Pass more SPI options to FSP.

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32791

Change subject: soc/intel/cannonlake: Pass more SPI options to FSP.
......................................................................

soc/intel/cannonlake: Pass more SPI options to FSP.

Add the ability for the device tree to set CsEnable, CsPolarity, and
DefaultCsOutput parameters to the FSP.

BUG=b:130329260
BRANCh=none
TEST=Compiles.

Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/serialio.h
3 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/32791/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2b2a51f..c3f3023 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -338,6 +338,17 @@
     */
    uint8_t SerialIoDevMode[PchSerialIoIndexMAX];

+	/* 0 = Active low CS, 1 = Active high CS */
+	uint8_t SerialIoSpi0CsPolarity[2];
+	uint8_t SerialIoSpi1CsPolarity[2];
+	uint8_t SerialIoSpi2CsPolarity[2];
+	/* 0 = GPIO, 1 = Chip select */
+	uint8_t SerialIoSpi0CsEnable[2];
+	uint8_t SerialIoSpi1CsEnable[2];
+	uint8_t SerialIoSpi2CsEnable[2];
+	/* Default CS as output; 0 = CS0, 1 = CS1 */
+	uint8_t SerialIoSpiDefaultCsOutput[3];
+
    /* GPIO SD card detect pin */
    unsigned int sdcard_cd_gpio;

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index cc01d10..dd5e2c4 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -86,6 +86,20 @@
    	params->SerialIoUartMode[i] =
    			get_param_value(config, dev_offset);
    }
+
+	for (i = 0; i < 2; i++) {
+		params->SerialIoSpi0CsPolarity[i] =
+			config->SerialIoSpi0CsPolarity[i];
+		params->SerialIoSpi1CsPolarity[i] =
+			config->SerialIoSpi1CsPolarity[i];
+		params->SerialIoSpi2CsPolarity[i] =
+			config->SerialIoSpi2CsPolarity[i];
+	}
+
+	for (i = 0; i < 3; i++) {
+		params->SerialIoSpiDefaultCsOutput[i] =
+			config->SerialIoSpiDefaultCsOutput[i];
+	}
 }
 #else
 static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params)
diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h
index c92bd2d..5ce4a80 100644
--- a/src/soc/intel/cannonlake/include/soc/serialio.h
+++ b/src/soc/intel/cannonlake/include/soc/serialio.h
@@ -54,4 +54,19 @@
    PchSerialIoIndexMAX
 } PCH_SERIAL_IO_CONTROLLER;

+typedef enum {
+	PchSerialIoCsActiveLow,
+	PchSerialIoCsActiveHigh,
+} PCH_SPI_CS_ACTIVE_MODE;
+
+typedef enum {
+	PchSerialIoCsGpio,
+	PchSerialIoCsEnable,
+} PCH_SPI_CS_ENABLE_MODE;
+
+typedef enum {
+	PchSerialIoCS0,
+	PchSerialIoCS1,
+} PCH_SPI_CS_SELECT;
+
 #endif