Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46133 )
Change subject: sb/intel/lynxpoint: Enable/disable AER via Kconfig ......................................................................
sb/intel/lynxpoint: Enable/disable AER via Kconfig
Several changes[1][2] to the Linux kernel now enable ASPM/AER for the rt8169 network driver, for which it was previously disabled. This, coupled with the southbridge enabling AER for all PCIe devices, has resulted in a large amount of AER timeout errors in the kernel log for boards which utilize the rt8169 for on-board Ethernet (e.g., google/beltino). While performance is not impacted, the errors do accumulate.
To mitigate this, guard AER enablement via Kconfig, select it by default (as to maintain current default behavior), and allow boards which need to disable it to do so (implemented in subsequent commits).
This implementation is derived from that in soc/intel/broadwell.
Test: build/boot google/beltino variants with AER disabled (CB:46136), verify dmesg log free of AER timeout errors.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=... [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=...
Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8 Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46133 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/pcie.c 2 files changed, 9 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index c104cbb..43f8bce 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -58,4 +58,8 @@ If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback.
+config PCIEXP_AER + bool + default y + endif diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 35ce5c47..077dcd6 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -670,8 +670,11 @@ /* Set EOI forwarding disable. */ pci_or_config32(dev, 0xd4, 1 << 1);
- /* Set something involving advanced error reporting. */ - pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); + /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ + if (CONFIG(PCIEXP_AER)) + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001); + else + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29));
if (is_lp) pci_or_config32(dev, 0x100, 1 << 29);