[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Init SSPM

[tinghan shen (Code Review)]

tinghan shen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47786 )

Change subject: soc/mediatek/mt8192: Init SSPM
......................................................................

soc/mediatek/mt8192: Init SSPM

SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.

Signed-off-by: TingHan.Shen 
Change-Id: Ia834852af50e9e7e1b1222ed1e2be20e43139c62
---
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/sspm.h
M src/soc/mediatek/mt8192/soc.c
A src/soc/mediatek/mt8192/sspm.c
5 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/47786/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 5d1c0ae..11588c8 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -51,6 +51,7 @@
 ramstage-y += devapc.c
 ramstage-y += mcupm.c
 ramstage-y += soc.c
+ramstage-y += sspm.c
 ramstage-y += ufs.c
 ramstage-y += ../common/mtlib.c
 ramstage-y += ../common/timer.c
@@ -74,6 +75,11 @@
 spm_firmware.bin-type := raw
 spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG)

+cbfs-files-y += sspm.bin
+sspm.bin-file := $(MT8192_BLOB_DIR)/sspm.bin
+sspm.bin-type := raw
+sspm.bin-compression := $(CBFS_COMPRESS_FLAG)
+
 cbfs-files-y += mcupm.bin
 mcupm.bin-file := $(MT8192_BLOB_DIR)/mcupm.bin
 mcupm.bin-type := raw
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index eb75823..397fa29 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -33,6 +33,8 @@
    EMI_BASE		= IO_PHYS + 0x00219000,
    EMI_MPU_BASE		= IO_PHYS + 0x00226000,
    DRAMC_CHA_AO_BASE	= IO_PHYS + 0x00230000,
+	SSPM_SRAM_BASE		= IO_PHYS + 0x00400000,
+	SSPM_CFG_BASE		= IO_PHYS + 0x00440000,
    AUXADC_BASE		= IO_PHYS + 0x01001000,
    DPM_PM_SRAM_BASE	= IO_PHYS + 0x00900000,
    DPM_DM_SRAM_BASE	= IO_PHYS + 0x00920000,
diff --git a/src/soc/mediatek/mt8192/include/soc/sspm.h b/src/soc/mediatek/mt8192/include/soc/sspm.h
new file mode 100644
index 0000000..5749fa4
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/sspm.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_SSPM_H
+#define SOC_MEDIATEK_MT8192_SSPM_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8192_sspm_regs {
+	u32 sw_rstn;
+};
+static struct mt8192_sspm_regs *const mt8192_sspm = (void *)SSPM_CFG_BASE;
+void sspm_init(void);
+#endif  /* SOC_MEDIATEK_MT8192_SSPM_H */
diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c
index 5a2fa37..883f4dc 100644
--- a/src/soc/mediatek/mt8192/soc.c
+++ b/src/soc/mediatek/mt8192/soc.c
@@ -5,6 +5,7 @@
 #include <soc/emi.h>
 #include <soc/mcupm.h>
 #include <soc/mmu_operations.h>
+#include <soc/sspm.h>
 #include <soc/ufs.h>
 #include <symbols.h>

@@ -18,6 +19,7 @@
    mtk_mmu_disable_l2c_sram();
    dapc_init();
    mcupm_init();
+	sspm_init();
    ufs_disable_refclk();
 }

diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c
new file mode 100644
index 0000000..a555d76
--- /dev/null
+++ b/src/soc/mediatek/mt8192/sspm.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/mtlib_common.h>
+#include <soc/sspm.h>
+
+void sspm_init(void)
+{
+	const char *sspm_file_name = "sspm.bin";
+
+	if (load_blob_file(sspm_file_name, SSPM_SRAM_BASE) == CB_SUCCESS) {
+		write32(&mt8192_sspm->sw_rstn, 0x1);
+	}
+}