Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS type 11 OEM data ......................................................................
mb/ocp/tiogapass: Populate SMBIOS type 11 OEM data
1. Populate SMBIOS type 11 OEM data according to OEM specification. 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC.
Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin johnny_lin@wiwynn.com
Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 4 files changed, 111 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/1
diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index 27370fd..33ae2ff 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -15,6 +15,7 @@
bootblock-y += bootblock.c ramstage-y += ramstage.c +ramstage-y += ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c new file mode 100644 index 0000000..7d98c0c --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <console/console.h> +#include "ipmi.h" + +void ipmi_set_ppin(struct ppin_req *req) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) req, sizeof(*req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return; + } + printk(BIOS_INFO, "IPMI Set PPIN done.\n"); +} diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h new file mode 100644 index 0000000..f8a98c9 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef TIOGAPASS_IPMI_H +#define TIOGAPASS_IPMI_H +#include <types.h> +#include <drivers/ipmi/ipmi_ops.h> + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 + +#define BMC_KCS_BASE 0xca2 + +/* PPIN for 2 CPU IPMI request */ +struct ppin_req { + uint32_t CPU0lo; + uint32_t CPU0hi; + uint32_t CPU1lo; + uint32_t CPU1hi; +} __packed; +/* Send CPU0 and CPU1 PPIN to BMC */ +void ipmi_set_ppin(struct ppin_req *req); +#endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 4820ed4..61d6aef 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -16,17 +16,17 @@ #include <bootstate.h> #include <gpio.h> #include <soc/lewisburg_pch_gpio_defs.h> +#include <soc/msr.h> #include <smbios.h> #include <drivers/ipmi/ipmi_ops.h> +#include "ipmi.h"
#define FRU_DEVICE_ID 0 -#define BMC_KCS_BASE 0xca2
static struct fru_info_str fru_strings;
void mainboard_silicon_init_params(FSPS_UPD *params) { - read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); }
/* Override SMBIOS type 1 data. */ @@ -148,4 +148,65 @@ gpio_output(GPP_B20, 0); }
+/* Override SMBIOS type 11 OEM string */ +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ppin[17]; + char blank[] = " "; + + /* Add OEM string 1 to 3 */ + if (*fru_strings.board_info.board_custom != NULL) + t->count = smbios_add_string(t->eos, *fru_strings.board_info.board_custom); + else + t->count = smbios_add_string(t->eos, blank); + if (*fru_strings.prod_info.product_custom != NULL) + t->count = smbios_add_string(t->eos, *fru_strings.prod_info.product_custom); + else + t->count = smbios_add_string(t->eos, blank); + + if (*(fru_strings.prod_info.product_custom + 1) != NULL) + t->count = smbios_add_string(t->eos, + *(fru_strings.prod_info.product_custom + 1)); + else + t->count = smbios_add_string(t->eos, blank); + + /* Add blank for OEM String 4 */ + t->count = smbios_add_string(t->eos, blank); + /* Add CPU0 and CPU1 PPIN to OEM string 5 and 6. */ + snprintf(ppin, sizeof(ppin), "%x%x", xeon_sp_ppin[0].hi, xeon_sp_ppin[0].lo); + t->count = smbios_add_string(t->eos, ppin); + snprintf(ppin, sizeof(ppin), "%x%x", xeon_sp_ppin[1].hi, xeon_sp_ppin[1].lo); + t->count = smbios_add_string(t->eos, ppin); + /* Add OEM string 7 */ + if (*(fru_strings.board_info.board_custom + 1) != NULL) + t->count = smbios_add_string(t->eos, + *(fru_strings.board_info.board_custom + 1)); + else + t->count = smbios_add_string(t->eos, blank); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = mainboard_smbios_strings, + + read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); +} + +static void mainboard_final(void *chip_info) +{ + struct ppin_req req; + + req.CPU0lo = xeon_sp_ppin[0].lo; + req.CPU0hi = xeon_sp_ppin[0].hi; + req.CPU1lo = xeon_sp_ppin[1].lo; + req.CPU1hi = xeon_sp_ppin[1].hi; + /* Set PPIN to BMC */ + ipmi_set_ppin(&req); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);