[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: FSP UPD update

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32026 )

Change subject: soc/intel/cannonlake: FSP UPD update
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
PS1, Line 169: PchPmSlpS0VmRuntimeControl
> Isn't this dependent on the mainboard design? i.e. […]

I agree with Furquan and I don't believe that's debug/validation thing.