Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46393
to review the following change.
Change subject: soc/mediatek/mt8192: Add dpm loader ......................................................................
soc/mediatek/mt8192: Add dpm loader
BUG=none TEST=Boots correctly on Asurada
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 --- M src/mainboard/google/asurada/mainboard.c M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dpm.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dpm.h 5 files changed, 136 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46393/1
diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 7b3ef22..677e917 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/mmio.h> #include <lib.h> +#include <soc/dpm.h> #include <soc/gpio_common.h> #include <soc/spm.h> #include <soc/usb.h> @@ -79,6 +80,9 @@
register_reset_to_bl31();
+ if (dpm_init()) + printk(BIOS_ERR, "dpm init fail, system can't do DVFS switch\n"); + if (spm_init()) printk(BIOS_ERR, "spm init fail, system suspend may stuck\n"); } diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 59d105c..5fc90a8 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += dpm.c ramstage-y += spm.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c @@ -48,6 +49,16 @@
MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192
+cbfs-files-y += dpm.dm +dpm.dm-file := $(MT8192_BLOB_DIR)/dpm.dm +dpm.dm-type := raw +dpm.dm-compression := $(CBFS_COMPRESS_FLAG) + +cbfs-files-y += dpm.pm +dpm.pm-file := $(MT8192_BLOB_DIR)/dpm.pm +dpm.pm-type := raw +dpm.pm-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += spm_firmware.bin spm_firmware.bin-file := $(MT8192_BLOB_DIR)/spm_firmware.bin spm_firmware.bin-type := raw diff --git a/src/soc/mediatek/mt8192/dpm.c b/src/soc/mediatek/mt8192/dpm.c new file mode 100644 index 0000000..7e018b5 --- /dev/null +++ b/src/soc/mediatek/mt8192/dpm.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/dpm.h> +#include <timer.h> + +#define DM_BUF_SIZE (2 * KiB) +#define PM_BUF_SIZE (20 * KiB) + +static u8 dpm_dm_bin[DM_BUF_SIZE] __aligned(8); +static u8 dpm_pm_bin[PM_BUF_SIZE] __aligned(8); +static void *dpm_pm_reg = (void *)DPM_PM_SRAM_BASE; +static void *dpm_dm_reg = (void *)DPM_DM_SRAM_BASE; + +static int dpm_load_firmware(void) +{ + const char *dm_file_name = "dpm.dm"; + const char *pm_file_name = "dpm.pm"; + size_t dm_file_size, pm_file_size; + + dm_file_size = cbfs_boot_load_file(dm_file_name, dpm_dm_bin, + sizeof(dpm_dm_bin), CBFS_TYPE_RAW); + if (dm_file_size == 0) { + printk(BIOS_ERR, "binary %s not found\n", dm_file_name); + return -1; + } + + pm_file_size = cbfs_boot_load_file(pm_file_name, dpm_pm_bin, + sizeof(dpm_pm_bin), CBFS_TYPE_RAW); + if (pm_file_size == 0) { + printk(BIOS_ERR, "binary %s not found\n", pm_file_name); + return -2; + } + printk(BIOS_INFO, "dm_file_size:%d, pm_file_size:%d\n", + (int)dm_file_size, (int)pm_file_size); + + /* config DPM SRAM layout */ + write32(&mtk_dpm->sw_rstn, read32(&mtk_dpm->sw_rstn) | 0x10000000); + + /* copy PM DM to DPM_SRAM */ + memcpy(dpm_pm_reg, dpm_pm_bin, pm_file_size); + memcpy(dpm_dm_reg, dpm_dm_bin, dm_file_size); + + /* write bootargs */ + write32(&mtk_dpm->twam_window_len, 0x0); + write32(&mtk_dpm->twam_mon_type, 0x0); + + /* free RST */ + write32(&mtk_dpm->sw_rstn, read32(&mtk_dpm->sw_rstn) | 0x1); + + return 0; +} + +int dpm_init(void) +{ + struct stopwatch sw; + stopwatch_init(&sw); + + if (dpm_load_firmware()) { + printk(BIOS_ERR, "DPM: firmware is not ready\n"); + return -1; + } + + printk(BIOS_INFO, "DPM: load finish in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + return 0; +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h old mode 100755 new mode 100644 index 9864e5b..5f49fe5 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -29,6 +29,9 @@ PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, AUXADC_BASE = IO_PHYS + 0x01001000, + DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, + DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, + DPM_CFG_BASE = IO_PHYS + 0x00940000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8192/include/soc/dpm.h b/src/soc/mediatek/mt8192/include/soc/dpm.h new file mode 100644 index 0000000..5763dab --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dpm.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DPM_H__ +#define __SOC_MEDIATEK_MT8192_DPM_H__ + +#include <soc/addressmap.h> +#include <stdint.h> +#include <types.h> + +#define DPM_DM_OFFSET 0x8000 /* 32KB */ + +struct dpm_regs { + u32 sw_rstn; + u32 rsvd_0[3072]; + u32 mclk_div; + u32 rsvd_1[3071]; + u32 twam_window_len; + u32 twam_mon_type; + u32 rsvd_2[1022]; + u32 low_power_cfg_0; + u32 low_power_cfg_1; + u32 rsvd_3[1]; + u32 fsm_out_ctrl_0; + u32 rsvd_4[8]; + u32 fsm_cfg_1; + u32 low_power_cfg_3; + u32 dfd_dbug_0; + u32 rsvd_5[28]; + u32 status_4; +}; + +check_member(dpm_regs, mclk_div, 0x3004); +check_member(dpm_regs, twam_window_len, 0x6004); +check_member(dpm_regs, low_power_cfg_0, 0x7004); +check_member(dpm_regs, low_power_cfg_1, 0x7008); +check_member(dpm_regs, fsm_out_ctrl_0, 0x7010); +check_member(dpm_regs, fsm_cfg_1, 0x7034); +check_member(dpm_regs, low_power_cfg_3, 0x7038); +check_member(dpm_regs, dfd_dbug_0, 0x703C); +check_member(dpm_regs, status_4, 0x70B0);; + +int dpm_init(void); + +#define mtk_dpm ((struct dpm_regs *)DPM_CFG_BASE) + +#endif /* __SOC_MEDIATEK_MT8192_DPM_H__ */