Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50980 )
Change subject: mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17 ......................................................................
mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc 4 files changed, 10 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 9cb8640..295e1b1 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -15,7 +15,8 @@ /* ADL-P DDR5 RVPs */ ADL_P_DDR5 = 0x12, /* ADL-P LPDDR5 RVP */ - ADL_P_LP5 = 0x13, + ADL_P_LP5_1 = 0x13, + ADL_P_LP5_2 = 0x17, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 5a7fa57..6f158a0 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -171,7 +171,8 @@ return &ddr4_mem_config; case ADL_P_DDR5: return &ddr5_mem_config; - case ADL_P_LP5: + case ADL_P_LP5_1: + case ADL_P_LP5_2: return &lp5_mem_config; default: die("unsupported board id : 0x%x\n", board_id); diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index c95d469..6ae5c17 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -57,7 +57,8 @@ break; case ADL_P_LP4_1: case ADL_P_LP4_2: - case ADL_P_LP5: + case ADL_P_LP5_1: + case ADL_P_LP5_2: memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated); break; default: diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 10ce42e..6e6709f 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -4,3 +4,7 @@ SPD_SOURCES += empty # 0b001 SPD_SOURCES += empty # 0b002 SPD_SOURCES += adlrvp_lp5 # 0b003 +SPD_SOURCES += empty # 0b004 +SPD_SOURCES += empty # 0b005 +SPD_SOURCES += empty # 0b006 +SPD_SOURCES += adlrvp_lp5 # 0b007