[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Lock SPI BIOS controls

[Marc Jones (Code Review)]

Attention is currently required from: Jonathan Zhang, Johnny Lin, Paul Menzel, Patrick Rudolph.
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51227 )

Change subject: soc/intel/xeon_sp: Lock SPI BIOS controls
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Patch Set 5: Verified-1

(3 comments)

Patchset:

PS5: 
I don't think we want to set EISS. It doesn't work with the coreboot/flashrom/vpd usage model.

File src/soc/intel/xeon_sp/lockdown.c:

https://review.coreboot.org/c/coreboot/+/51227/comment/2a6dc4df_bf3564e6 
PS5, Line 18: SPI_BC_LE
> Setting LE has no effect until you enable TCO SMIs. […]

Agreed, I don't think we want to enable the EISS. How did you know about the TCO SMIs? I was trying to figure this out from the register description.

https://review.coreboot.org/c/coreboot/+/51227/comment/8dc9c59d_4eaba8af 
PS5, Line 18: SPI_BC_EISS
> That would make it impossible to write VPDs as BIOS region will only be writable in SMM.

Ack