Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39491 )
Change subject: soc/intel/cannonlake/bootblock: Fix FSP CAR ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39491/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39491/3//COMMIT_MSG@9 PS3, Line 9: Fix FSP CAR on plaforms that have ROM_SIZE of 32MiB.
It doesn't boot, no output on serial.
I think the comment in the code is now pretty instructive: "CodeRegionSize must be smaller than or equal to 16MiB to not overlap with LAPIC or the CAR area at 0xfef00000."
Messing with LAPIC or CAR typically ends in having a bad time.
https://review.coreboot.org/c/coreboot/+/39491/1/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39491/1/src/soc/intel/cannonlake/bo... PS1, Line 32: #if CONFIG_ROM_SIZE > 16 * 1024 * 1024 : #define CODE_CACHE_SIZE (16 * 1024 * 1024) : #else : #define CODE_CACHE_SIZE CONFIG_ROM_SIZE : #endif
it could be defined by motherboard, but I don't see any issues marking the 16MiB as cached even if l […]
Done