[coreboot-gerrit] Patch merged into coreboot/master: 67481dd haswell: set TSEG as WB cacheable in romstage

the following patch was just integrated into master:
commit 67481ddc2e53cd3420fa8c723edb4fe47dccc196
Author: Aaron Durbin 
Date:   Fri Feb 15 15:08:37 2013 -0600

haswell: set TSEG as WB cacheable in romstage

The TSEG region is accessible until the SMM handler is relocated
    to that region. Set the region as cacheable in romstage so that it
    can be used for other purposes with fast access.

Change-Id: I92b83896e40bc26a54c2930e05c02492918e0874
    Signed-off-by: Aaron Durbin 
    Reviewed-on: http://review.coreboot.org/2803
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich

Build-Tested: build bot (Jenkins) at Tue Mar 19 06:58:30 2013, giving +1
Reviewed-By: Ronald G. Minnich  at Thu Mar 21 22:58:17 2013, giving +2
See http://review.coreboot.org/2803 for details.

-gerrit