Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36328 )
Change subject: [RFC] Documentation/fsp: Discuss FSP-S issues ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36328/4/Documentation/fsp/fsp-s_dis... File Documentation/fsp/fsp-s_discussion.md:
https://review.coreboot.org/c/coreboot/+/36328/4/Documentation/fsp/fsp-s_dis... PS4, Line 15: * `FSP-M`: Initializes the memory (DRAM) controller, among other
Frankly, FSP-M has begun to do more and more over the generations. […]
Besides memory init, FSP also does HSIO programming (plus related PCIe, SATA, xHCI init), some MEI messaging stuff, DMI init, overclocking stuff, some TXT init, Trace Hub init... The list goes on.
FSP-S does some PCIe, SATA and USB configuration (IIRC, link training, capability programming and function swapping) that isn't about PHY tuning, some IOAPIC/HPET config (which I did in CB:35170 and is just programming a few registers), HDA config, configuring thermal throttling stuff, power management init, Serial I/O init, interrupt routing, CIO2 (camera) config, SCS (SD/eMMC) config, flash protection settings, some more MEI messages to signal End Of POST, BIOS Guard setup, SGX setup, CPU power management and VR settings...
The difference between FSP-M stuff and FSP-S stuff is that the former touches PHY stuff much more than the latter. And stuff surrounding PHY technology is usually kept very secret. Maybe PHYs are made out of arcane magic?
https://review.coreboot.org/c/coreboot/+/36328/4/Documentation/fsp/fsp-s_dis... PS4, Line 126: FSP Switches SAI : ----------------
Interesting. While the BIOS Spec doesn't mention any specific point […]
Reminds me of something called M-Check, which happens at some point after memory is initialized and consists of locking down lots of stuff.