Attention is currently required from: Arthur Heymans, Alexander Couzens, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 )
Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE ......................................................................
Patch Set 1:
(1 comment)
File src/cpu/intel/socket_p/Kconfig:
https://review.coreboot.org/c/coreboot/+/52942/comment/5b3557f0_96c74cee PS1, Line 16: default 0x10000
CPU_INTEL_SOCKET_BGA956 and CPU_INTEL_SOCKET_M use 0x8000 here, and are never used with NO_CBFS_MCACHE. I'd simply drop `select NO_CBFS_MCACHE` from t400.
config.lenovo_t400_vboot_and_debug fails to build then :-/
Why is this not mentioned in the commit message?
I would expect that the same settings would not build on X200 either. And IIRC you have an X200, so you could test if doubling DCACHE_RAM_SIZE works on it.
I'm pretty sure cache won't be an issue but I can also strip down that config. Any thoughts? Obviously t400 should not miss out on cbfs_mcache because of a probably not booting debug buildtest.
I agree that it should be safe to increase this, but I'm somewhat worried because the coreboot 4.14 release is scheduled for the 10th (in three days).
The lowest bound for L2 cache size on Socket P is 512 KiB: https://www.cpu-world.com/CPUs/Celeron_Dual-Core/Intel-Mobile%20Celeron%20Du...