[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer/variant/lindar: Modify PL2 value.

[Kevin Chang (Code Review)]

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50874 )

Change subject: mb/google/volteer/variant/lindar: Modify PL2 value.
......................................................................

mb/google/volteer/variant/lindar: Modify PL2 value.

Modify PL2 to 25W from 60W.

BUG=b:180531780
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS

Signed-off-by: Kevin Chang 
Change-Id: I848a8af1b86165c0bdd10804b470416c1cad9710
---
M src/mainboard/google/volteer/variants/lindar/overridetree.cb
1 file changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/50874/1

diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
index 3140b85..49d4a85 100644
--- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
@@ -13,6 +13,15 @@

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0

+	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 25,
+	}"
+	register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 25,
+	}"
+
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
    #+-------------------+---------------------------+
@@ -58,6 +67,21 @@
    	[PchSerialIoIndexI2C5]  = PchSerialIoPci,
    }"
    device domain 0 on
+		device ref dptf on
+			# DPTF Policy for Eldrid board
+			chip drivers/intel/dptf
+				## Power Limits Control
+				# PL2 is fixed at 25W, avg over 28-32s interval
+				register "controls.power_limits" = "{
+					.pl2 = {.min_power = 15000,
+						.max_power = 25000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 1000,}}"
+
+				device generic 0 on end
+			end
+		end
    	# Baseboard has these on, so they must be disabled here.
    	device ref tbt_pcie_rp0 off end
    	device ref tbt_pcie_rp1 off end