Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Sridhar Siricilla, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 )
Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 13: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/55364/comment/cc405ed4_5005ca5a
PS13, Line 135: timestamp_add_now(TS_BEFORE_CSE_FW_SYNC);
nit: you can submit timestamp CL separately if you wish ?
that way this CL is just moving things from post memory state to pre memory state.
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