[coreboot-gerrit] [S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs

[Vince Liu (Code Review)]

Attention is currently required from: Hung-Te Lin, Vince Liu.

Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86538?usp=email

to look at the new patch set (#3).

Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
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soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs

In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB.

BUG=b:379008996
BRANCH=none
TEST=booted successfully

Signed-off-by: Vince Liu 
Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4
---
M src/soc/mediatek/mt8189/gpio.c
1 file changed, 37 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86538/3