Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7326
-gerrit
commit 6b30ed3581601bc2bf8a299ff7e75e47753c8869 Author: Vladimir Serbinenko phcoder@gmail.com Date: Tue Nov 4 21:09:23 2014 +0100
ibexpeak, bd82x6x: Move to implicit length patching
Change-Id: I43eef7f97398d7c4c3f8d9790920fa4402019dd7 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/cpu/intel/fsp_model_206ax/acpi.c | 112 ++++++++++++++------------------ src/cpu/intel/model_2065x/acpi.c | 100 +++++++++++++--------------- src/cpu/intel/model_206ax/acpi.c | 102 +++++++++++++---------------- src/cpu/intel/speedstep/acpi.c | 32 ++++----- src/southbridge/intel/bd82x6x/lpc.c | 8 +-- src/southbridge/intel/fsp_bd82x6x/lpc.c | 8 +-- src/southbridge/intel/ibexpeak/lpc.c | 8 +-- 7 files changed, 161 insertions(+), 209 deletions(-)
diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index 28aeb43..57af836 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -48,10 +48,10 @@ static int get_cores_per_package(void) return cores; }
-static int generate_cstate_entries(acpi_cstate_t *cstates, +static void generate_cstate_entries(acpi_cstate_t *cstates, int c1, int c2, int c3) { - int length, cstate_count = 0; + int cstate_count = 0;
/* Count number of active C-states */ if (c1 > 0) @@ -61,74 +61,70 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, if (c3 > 0) ++cstate_count; if (!cstate_count) - return 0; + return;
- length = acpigen_write_package(cstate_count + 1); - length += acpigen_write_byte(cstate_count); + acpigen_write_package(cstate_count + 1); + acpigen_write_byte(cstate_count);
/* Add an entry if the level is enabled */ if (c1 > 0) { cstates[c1].ctype = 1; - length += acpigen_write_CST_package_entry(&cstates[c1]); + acpigen_write_CST_package_entry(&cstates[c1]); } if (c2 > 0) { cstates[c2].ctype = 2; - length += acpigen_write_CST_package_entry(&cstates[c2]); + acpigen_write_CST_package_entry(&cstates[c2]); } if (c3 > 0) { cstates[c3].ctype = 3; - length += acpigen_write_CST_package_entry(&cstates[c3]); + acpigen_write_CST_package_entry(&cstates[c3]); }
- acpigen_patch_len(length - 1); - return length; + acpigen_pop_len(); }
-static int generate_C_state_entries(void) +static void generate_C_state_entries(void) { struct cpu_info *info; struct cpu_driver *cpu; - int len, lenif; struct device *lapic; struct cpu_intel_fsp_model_206ax_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */ lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); if (!lapic) - return 0; + return; conf = lapic->chip_info; if (!conf) - return 0; + return;
/* Find CPU map of supported C-states */ info = cpu_info(); if (!info) - return 0; + return; cpu = find_cpu_driver(info->cpu); if (!cpu || !cpu->cstates) - return 0; + return;
- len = acpigen_emit_byte(0x14); /* MethodOp */ - len += acpigen_write_len_f(); /* PkgLength */ - len += acpigen_emit_namestring("_CST"); - len += acpigen_emit_byte(0x00); /* No Arguments */ + acpigen_emit_byte(0x14); /* MethodOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("_CST"); + acpigen_emit_byte(0x00); /* No Arguments */
/* If running on AC power */ - len += acpigen_emit_byte(0xa0); /* IfOp */ - lenif = acpigen_write_len_f(); /* PkgLength */ - lenif += acpigen_emit_namestring("PWRS"); - lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ - lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower, + acpigen_emit_byte(0xa0); /* IfOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_acpower, conf->c2_acpower, conf->c3_acpower); - acpigen_patch_len(lenif - 1); - len += lenif; + acpigen_pop_len();
/* Else on battery power */ - len += acpigen_emit_byte(0xa4); /* ReturnOp */ - len += generate_cstate_entries(cpu->cstates, conf->c1_battery, + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_battery, conf->c2_battery, conf->c3_battery); - acpigen_patch_len(len - 1); - return len; + acpigen_pop_len(); }
static acpi_tstate_t tss_table_fine[] = { @@ -160,31 +156,27 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, };
-static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
/* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC();
/* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\TLVL"); + acpigen_write_TPC("\TLVL");
/* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; }
static int calculate_power(int tdp, int p1_ratio, int ratio) @@ -208,9 +200,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; }
-static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -245,16 +236,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + acpigen_write_PSD_package(core, cores_per_package, coord_type);
/* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS");
/* Determine ratio points */ ratio_step = PSS_RATIO_STEP; @@ -267,13 +258,13 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2);
msr = rdmsr(MSR_TURBO_RATIO_LIMIT); ratio_turbo = msr.lo & 0xff;
/* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -282,11 +273,11 @@ static int generate_P_state_entries(int core, int cores_per_package) ratio_turbo << 8); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); }
/* First regular entry is max non-turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -302,7 +293,7 @@ static int generate_P_state_entries(int core, int cores_per_package) power = calculate_power(power_max, ratio_max, ratio); clock = ratio * SANDYBRIDGE_BCLK;
- len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -312,15 +303,11 @@ static int generate_P_state_entries(int core, int cores_per_package) }
/* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); }
void generate_cpu_entries(void) { - int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); @@ -337,23 +324,22 @@ void generate_cpu_entries(void) }
/* Generate processor _PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
/* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( cpuID-1, cores_per_package);
/* Generate C-state tables */ - len_pr += generate_C_state_entries(); + generate_C_state_entries();
/* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( cpuID-1, cores_per_package);
- len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 870020f..bfe801d 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -48,10 +48,10 @@ static int get_cores_per_package(void) return cores; }
-static int generate_cstate_entries(acpi_cstate_t *cstates, +static void generate_cstate_entries(acpi_cstate_t *cstates, int c1, int c2, int c3) { - int length, cstate_count = 0; + int cstate_count = 0;
/* Count number of active C-states */ if (c1 > 0) @@ -61,74 +61,70 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, if (c3 > 0) ++cstate_count; if (!cstate_count) - return 0; + return;
- length = acpigen_write_package(cstate_count + 1); - length += acpigen_write_byte(cstate_count); + acpigen_write_package(cstate_count + 1); + acpigen_write_byte(cstate_count);
/* Add an entry if the level is enabled */ if (c1 > 0) { cstates[c1].ctype = 1; - length += acpigen_write_CST_package_entry(&cstates[c1]); + acpigen_write_CST_package_entry(&cstates[c1]); } if (c2 > 0) { cstates[c2].ctype = 2; - length += acpigen_write_CST_package_entry(&cstates[c2]); + acpigen_write_CST_package_entry(&cstates[c2]); } if (c3 > 0) { cstates[c3].ctype = 3; - length += acpigen_write_CST_package_entry(&cstates[c3]); + acpigen_write_CST_package_entry(&cstates[c3]); }
- acpigen_patch_len(length - 1); - return length; + acpigen_pop_len(); }
-static int generate_C_state_entries(void) +static void generate_C_state_entries(void) { struct cpu_info *info; struct cpu_driver *cpu; - int len, lenif; struct device *lapic; struct cpu_intel_model_2065x_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */ lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); if (!lapic) - return 0; + return; conf = lapic->chip_info; if (!conf) - return 0; + return;
/* Find CPU map of supported C-states */ info = cpu_info(); if (!info) - return 0; + return; cpu = find_cpu_driver(info->cpu); if (!cpu || !cpu->cstates) - return 0; + return;
- len = acpigen_emit_byte(0x14); /* MethodOp */ - len += acpigen_write_len_f(); /* PkgLength */ - len += acpigen_emit_namestring("_CST"); - len += acpigen_emit_byte(0x00); /* No Arguments */ + acpigen_emit_byte(0x14); /* MethodOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("_CST"); + acpigen_emit_byte(0x00); /* No Arguments */
/* If running on AC power */ - len += acpigen_emit_byte(0xa0); /* IfOp */ - lenif = acpigen_write_len_f(); /* PkgLength */ - lenif += acpigen_emit_namestring("PWRS"); - lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ - lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_patch_len(lenif - 1); - len += lenif; + acpigen_emit_byte(0xa0); /* IfOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_acpower, + conf->c2_acpower, conf->c3_acpower); + acpigen_pop_len();
/* Else on battery power */ - len += acpigen_emit_byte(0xa4); /* ReturnOp */ - len += generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_patch_len(len - 1); - return len; + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_battery, + conf->c2_battery, conf->c3_battery); + acpigen_pop_len(); }
static acpi_tstate_t tss_table_fine[] = { @@ -208,9 +204,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; }
-static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, num_entries; int ratio, power, clock, clock_max; @@ -242,16 +237,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = 25000;
/* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + acpigen_write_PSD_package(core, cores_per_package, coord_type);
/* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS");
/* Determine ratio points */ ratio_step = PSS_RATIO_STEP; @@ -264,13 +259,13 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2);
msr = rdmsr(MSR_TURBO_RATIO_LIMIT); ratio_turbo = msr.lo & 0xff;
/* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -279,11 +274,11 @@ static int generate_P_state_entries(int core, int cores_per_package) ratio_turbo); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); }
/* First regular entry is max non-turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -299,7 +294,7 @@ static int generate_P_state_entries(int core, int cores_per_package) power = calculate_power(power_max, ratio_max, ratio); clock = ratio * NEHALEM_BCLK + ratio / 3;
- len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -309,15 +304,11 @@ static int generate_P_state_entries(int core, int cores_per_package) }
/* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); }
void generate_cpu_entries(void) { - int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); @@ -334,23 +325,22 @@ void generate_cpu_entries(void) }
/* Generate processor _PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
/* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( cpuID-1, cores_per_package);
/* Generate C-state tables */ - len_pr += generate_C_state_entries(); + generate_C_state_entries();
/* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( cpuID-1, cores_per_package);
- len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 21f9c3e..a801ec0 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -48,10 +48,10 @@ static int get_cores_per_package(void) return cores; }
-static int generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) +static void generate_cstate_entries(acpi_cstate_t *cstates, + int c1, int c2, int c3) { - int length, cstate_count = 0; + int cstate_count = 0;
/* Count number of active C-states */ if (c1 > 0) @@ -61,74 +61,70 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, if (c3 > 0) ++cstate_count; if (!cstate_count) - return 0; + return;
- length = acpigen_write_package(cstate_count + 1); - length += acpigen_write_byte(cstate_count); + acpigen_write_package(cstate_count + 1); + acpigen_write_byte(cstate_count);
/* Add an entry if the level is enabled */ if (c1 > 0) { cstates[c1].ctype = 1; - length += acpigen_write_CST_package_entry(&cstates[c1]); + acpigen_write_CST_package_entry(&cstates[c1]); } if (c2 > 0) { cstates[c2].ctype = 2; - length += acpigen_write_CST_package_entry(&cstates[c2]); + acpigen_write_CST_package_entry(&cstates[c2]); } if (c3 > 0) { cstates[c3].ctype = 3; - length += acpigen_write_CST_package_entry(&cstates[c3]); + acpigen_write_CST_package_entry(&cstates[c3]); }
- acpigen_patch_len(length - 1); - return length; + acpigen_pop_len(); }
-static int generate_C_state_entries(void) +static void generate_C_state_entries(void) { struct cpu_info *info; struct cpu_driver *cpu; - int len, lenif; struct device *lapic; struct cpu_intel_model_206ax_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */ lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); if (!lapic) - return 0; + return; conf = lapic->chip_info; if (!conf) - return 0; + return;
/* Find CPU map of supported C-states */ info = cpu_info(); if (!info) - return 0; + return; cpu = find_cpu_driver(info->cpu); if (!cpu || !cpu->cstates) - return 0; + return;
- len = acpigen_emit_byte(0x14); /* MethodOp */ - len += acpigen_write_len_f(); /* PkgLength */ - len += acpigen_emit_namestring("_CST"); - len += acpigen_emit_byte(0x00); /* No Arguments */ + acpigen_emit_byte(0x14); /* MethodOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("_CST"); + acpigen_emit_byte(0x00); /* No Arguments */
/* If running on AC power */ - len += acpigen_emit_byte(0xa0); /* IfOp */ - lenif = acpigen_write_len_f(); /* PkgLength */ - lenif += acpigen_emit_namestring("PWRS"); - lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ - lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_patch_len(lenif - 1); - len += lenif; + acpigen_emit_byte(0xa0); /* IfOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_acpower, + conf->c2_acpower, conf->c3_acpower); + acpigen_pop_len();
/* Else on battery power */ - len += acpigen_emit_byte(0xa4); /* ReturnOp */ - len += generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_patch_len(len - 1); - return len; + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_battery, + conf->c2_battery, conf->c3_battery); + acpigen_pop_len(); }
static acpi_tstate_t tss_table_fine[] = { @@ -208,9 +204,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; }
-static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -245,16 +240,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + acpigen_write_PSD_package(core, cores_per_package, coord_type);
/* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS");
/* Determine ratio points */ ratio_step = PSS_RATIO_STEP; @@ -267,13 +262,13 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2);
msr = rdmsr(MSR_TURBO_RATIO_LIMIT); ratio_turbo = msr.lo & 0xff;
/* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -282,11 +277,11 @@ static int generate_P_state_entries(int core, int cores_per_package) ratio_turbo << 8); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); }
/* First regular entry is max non-turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -302,7 +297,7 @@ static int generate_P_state_entries(int core, int cores_per_package) power = calculate_power(power_max, ratio_max, ratio); clock = ratio * SANDYBRIDGE_BCLK;
- len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ PSS_LATENCY_TRANSITION, /*lat1*/ @@ -312,15 +307,11 @@ static int generate_P_state_entries(int core, int cores_per_package) }
/* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); }
void generate_cpu_entries(void) { - int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); @@ -337,23 +328,22 @@ void generate_cpu_entries(void) }
/* Generate processor _PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( (cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
/* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( cpuID-1, cores_per_package);
/* Generate C-state tables */ - len_pr += generate_C_state_entries(); + generate_C_state_entries();
/* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( cpuID-1, cores_per_package);
- len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 98d1ee7..8a2bff1 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -82,18 +82,17 @@ static int get_fsb(void) return 600; }
-static int gen_pstate_entries(const sst_table_t *const pstates, +static void gen_pstate_entries(const sst_table_t *const pstates, const int cpuID, const int cores_per_package, const uint8_t coordination) { int i; - int len, len_ps; int frequency;
- len = acpigen_write_empty_PCT(); - len += acpigen_write_PSD_package( + acpigen_write_empty_PCT(); + acpigen_write_PSD_package( cpuID, cores_per_package, coordination); - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS");
const int fsb3 = get_fsb(); const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO( @@ -107,7 +106,7 @@ static int gen_pstate_entries(const sst_table_t *const pstates, printk(BIOS_DEBUG, "adding %x P-States between " "busratio %x and %x, ""incl. P0\n", pstates->num_states, min_ratio2 / 2, max_ratio2 / 2); - len_ps = acpigen_write_package(pstates->num_states); + acpigen_write_package(pstates->num_states); for (i = 0; i < pstates->num_states; ++i) { const sst_state_t *const pstate = &pstates->states[i]; /* Report frequency of turbo mode as that of HFM + 1. */ @@ -119,19 +118,14 @@ static int gen_pstate_entries(const sst_table_t *const pstates, frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/12; else frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/6; - len_ps += acpigen_write_PSS_package( + acpigen_write_PSS_package( frequency, pstate->power, 0, 0, SPEEDSTEP_ENCODE_STATE(*pstate), SPEEDSTEP_ENCODE_STATE(*pstate)); } - len_ps--; - acpigen_patch_len(len_ps); + acpigen_pop_len();
- len += acpigen_write_PPC(0); - - len += len_ps; - - return len; + acpigen_write_PPC(0); }
/** @@ -139,7 +133,6 @@ static int gen_pstate_entries(const sst_table_t *const pstates, */ void generate_cpu_entries(void) { - int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; @@ -171,21 +164,20 @@ void generate_cpu_entries(void) }
/* Generate processor _PR.CPUx. */ - len_pr = acpigen_write_processor( + acpigen_write_processor( cpuID * cores_per_package + coreID - 1, pcontrol_blk, plen);
/* Generate p-state entries. */ - len_pr += gen_pstate_entries(&pstates, cpuID, + gen_pstate_entries(&pstates, cpuID, cores_per_package, coordination);
/* Generate c-state entries. */ if (num_cstates > 0) - len_pr += acpigen_write_CST_package( + acpigen_write_CST_package( cstates, num_cstates);
- len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0e3a4f6..1e16eb2 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -680,8 +680,6 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion();
if (gnvs) { - int scopelen; - memset(gnvs, 0, sizeof (*gnvs));
acpi_create_gnvs(gnvs); @@ -700,9 +698,9 @@ static void southbridge_inject_dsdt(void) smm_setup_structures(gnvs, NULL, NULL);
/* Add it to DSDT. */ - scopelen = acpigen_write_scope("\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } }
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e5d63b6..d149824 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -639,8 +639,6 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion();
if (gnvs) { - int scopelen; - memset(gnvs, 0, sizeof (*gnvs));
acpi_create_gnvs(gnvs); @@ -650,9 +648,9 @@ static void southbridge_inject_dsdt(void) smm_setup_structures(gnvs, NULL, NULL);
/* Add it to DSDT. */ - scopelen = acpigen_write_scope("\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } }
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a833a3d..b08cb89 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -674,8 +674,6 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion();
if (gnvs) { - int scopelen; - memset(gnvs, 0, sizeof (*gnvs));
acpi_create_gnvs(gnvs); @@ -685,9 +683,9 @@ static void southbridge_inject_dsdt(void) smm_setup_structures(gnvs, NULL, NULL);
/* Add it to SSDT. */ - scopelen = acpigen_write_scope("\"); - scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_patch_len(scopelen - 1); + acpigen_write_scope("\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); } }