[coreboot-gerrit] [L] Change in coreboot[master]: src/*/post_code.h: Change post code prefix to POSTCODE

[Yuchen He (Code Review)]

Attention is currently required from: Eric Lai, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Paul Menzel, Raul Rangel, Yuchen He.

Hello Eric Lai, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Raul Rangel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/76044?usp=email

to look at the new patch set (#9).

The following approvals got outdated and were removed:
Code-Review+1 by Eric Lai, Code-Review+2 by Martin L Roth, Verified+1 by build bot (Jenkins)

Change subject: src/*/post_code.h: Change post code prefix to POSTCODE
......................................................................

src/*/post_code.h: Change post code prefix to POSTCODE

The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.

The files was changed by running the following bash script from the
top level directory.

header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
    src/include/cpu/intel/post_codes.h \
    src/soc/intel/common/block/include/intelblocks/post_codes.h"

array=`grep -r "#define POST_" $header | \
    tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`

for str in $array; do
    splitstr=`echo $str | cut -d '_' -f2-`
    grep -r $str src | cut -d ':' -f 1 | \
    	xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done

Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He 
---
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/non-evict/exit_car.S
M src/cpu/intel/car/p3/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/exit_car.S
M src/drivers/amd/agesa/cache_as_ram.S
M src/include/cpu/intel/post_codes.h
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/common/block/cpu/car/cache_as_ram.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/amd/common/block/include/amdblocks/post_codes.h
M src/soc/amd/common/psp_verstage/include/psp_post_code.h
M src/soc/amd/glinda/romstage.c
M src/soc/amd/mendocino/romstage.c
M src/soc/amd/phoenix/romstage.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/bootblock.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/post_codes.h
23 files changed, 159 insertions(+), 159 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/76044/9