[coreboot-gerrit] Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS

[Felix Singer (Code Review)]

Attention is currently required from: Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph, Tim Crawford, Sean Rhodes, SRIDHAR SIRICILLA, Tim Wawrzynczak, Evgeny Zinoviev, Felix Held.
 Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 )

Change subject: soc/intel: Allow enable/disable ME via CMOS
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Patch Set 89:

(2 comments)

File src/soc/intel/common/block/cse/cse.c:

https://review.coreboot.org/c/coreboot/+/52800/comment/06c197f3_5469ba43 
PS88, Line 1067: me_state
I would use another name here. While reading the code below, I thought this would be related to something of the me firmware but it's the value of the config option.

Something like this: config_me_state or option_me_state

https://review.coreboot.org/c/coreboot/+/52800/comment/0ba9e583_abffe832 
PS88, Line 1085: enable
> `disable_reply` ?

I would name this `state_reply`. Maybe also switch the words so that the reader recognizes that `reply_state` and `reply_size` are related.