[coreboot-gerrit] [M] Change in coreboot[master]: drivers/intel/fsp2_0: Update MRC cache in ramstage

[Angel Pons (Code Review)]

Attention is currently required from: Kangheui Won, Reka Norman, Tim Wawrzynczak, Paul Menzel, Julius Werner, Arthur Heymans, Andrey Petrov.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67669 )

Change subject: drivers/intel/fsp2_0: Update MRC cache in ramstage
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/67669/comment/a98b6cb9_f5b50679 
PS1, Line 18:
> > Yeah, I found that too and considered adding it there. […]

I think the FSP version gets passed to the MRC cache code so that it doesn't get reused after FSP gets updated. On older platforms without FSP, we just use a number that gets incremented whenever backwards compatibility cannot be guaranteed.