Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38691 )
Change subject: soc/amd/picasso: Enable cache in bootblock ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... File src/soc/amd/picasso/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 58: SYSCFG_MSR_MtrrFixDramEn What does this exactly do?
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 69: FLASH_BASE_ADDR What is this? Is the flash not mapped below 4GiB as usual? Can't we use CACHE_ROM_BASE/_SIZE?
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 69: CONFIG_ROM_SIZE What if CONFIG_ROM_SIZE is >16MiB?
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 74: _ebootblock - _bootblock Will there be a guarantee this is a power of 2?
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 75: MTRR_TYPE_WRBACK);
wasn't it always indent with tabs and align with spaces? or should i just indent the second half wit […]
I guess it complains if there are more than 7 spaces.