[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 13:
> CB:34995, adding TSEG WB is the least controversial and something that would get easily merged.
> It is also roughly half (~7 ms) of #1 vs #2 improvement (reaching payload) and needs to appear alone as the first commit of your patch train.

Done.