Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35026 )
Change subject: soc/intel/{cnl, icl}: Cache the TSEG region ......................................................................
Patch Set 2:
Patch Set 2:
#2 With POSTCAR_STAGE=y and (CB:34995 + CB: 35026) [romstage -> postcar -> ramstage]
Aug 23
Total Time: 818,078
Total Time till picking kernel: 818,078 Total Time till picking payload: 639,809
For this commit 36b7091 exactly, I want to see full 'cbmem -t' data as I am trying to figure out the mystery of timestamp 1100, where we seem to consistently loose 10ms if we gained 7ms earlier.
0:1st timestamp 12,859 5:start of verified boot 39,611 (26,752) 503:starting to initialize TPM 40,214 (602) 504:finished TPM initialization 78,129 (37,914) 505:starting to verify keyblock/preamble (RSA) 79,477 (1,348) 506:finished verifying keyblock/preamble (RSA) 94,209 (14,732) 507:starting to verify body (load+SHA2+RSA) 94,211 (2) 508:finished loading body (ignore for x86) 218,497 (124,285) 509:finished calculating body hash (SHA2) 237,400 (18,902) 510:finished verifying body signature (RSA) 240,012 (2,612) 511:starting TPM PCR extend 240,637 (624) 512:finished TPM PCR extend 256,116 (15,479) 513:starting locking TPM 256,117 (0) 514:finished locking TPM 264,444 (8,327) 6:end of verified boot 272,726 (8,282) 13:starting to load romstage 272,744 (18) 14:finished loading romstage 272,745 (0) 1:start of romstage 272,750 (5) 2:before ram initialization 272,793 (42) 950:calling FspMemoryInit 275,628 (2,835) 951:returning from FspMemoryInit 300,986 (25,358) 3:after ram initialization 304,318 (3,332) 4:end of romstage 306,148 (1,829) 100:start of postcar 307,039 (891) 101:end of postcar 307,039 (0) 8:starting to load ramstage 307,181 (141) 15:starting LZMA decompress (ignore for x86) 307,188 (7) 16:finished LZMA decompress (ignore for x86) 332,709 (25,520) 9:finished loading ramstage 332,813 (104) 550:starting to load Chrome OS VPD 332,886 (73) 10:start of ramstage 333,225 (338) 30:device enumeration 378,839 (45,614) 954:calling FspSiliconInit 387,354 (8,515) 955:returning from FspSiliconInit 475,359 (88,004) 40:device configuration 491,026 (15,667) 956:calling FspNotify(AfterPciEnumeration) 525,419 (34,393) 957:returning from FspNotify(AfterPciEnumeration) 525,727 (307) 50:device enable 525,915 (188) 60:device initialization 545,716 (19,800) 70:device setup done 578,491 (32,774) 75:cbmem post 579,000 (509) 80:write tables 579,141 (141) 15:starting LZMA decompress (ignore for x86) 582,037 (2,896) 16:finished LZMA decompress (ignore for x86) 582,298 (260) 85:finalize chips 582,920 (621) 90:load payload 596,851 (13,931) 15:starting LZMA decompress (ignore for x86) 597,138 (287) 16:finished LZMA decompress (ignore for x86) 645,026 (47,887) 958:calling FspNotify(ReadyToBoot) 645,536 (510) 959:returning from FspNotify(ReadyToBoot) 651,697 (6,161) 960:calling FspNotify(EndOfFirmware) 651,792 (95) 961:returning from FspNotify(EndOfFirmware) 652,199 (406) 99:selfboot jump 652,668 (469) 1000:depthcharge start 652,687 (18) 1002:RO vboot init 652,799 (112) 1020:vboot select&load kernel 652,803 (3) 1030:finished EC verification 672,980 (20,177) 1040:finished storage device initialization 674,068 (1,087) 1050:finished reading kernel from disk 681,173 (7,104) 1100:finished vboot kernel verification 828,455 (147,282) 1101:jumping to kernel 830,962 (2,506)
Total Time: 818,078