Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )
Change subject: binaryPI: implement C bootblock ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... File src/drivers/amd/agesa/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... PS8, Line 159: %esp
Where are the AP's stack? You probably want some linker symbol region to assert that that it does no […]
It can be found in src/vendorcode/amd/pi/<family>/binaryPI/gcccar.inc for each family: For example 00730F01: BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
Procedure with stack alignment is exactly the same as for ROMCC_BOOTBLOCK: https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache...