Attention is currently required from: Angel Pons, Riku Viitanen.
Nicholas Chin has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email )
Change subject: mb/asrock: Add Z77 Extreme4 ......................................................................
Patch Set 10:
(13 comments)
File src/mainboard/asrock/z77_extreme4/Kconfig:
https://review.coreboot.org/c/coreboot/+/85772/comment/1be16ffe_bc3f39a3?usp... : PS10, Line 27: int Type not needed here as it's defined in `sb/intel/bd82x6x/Kconfig`
File src/mainboard/asrock/z77_extreme4/devicetree.cb:
PS10: Some nits based on reviews of some of my ports. I'm not particularly picky about these.
https://review.coreboot.org/c/coreboot/+/85772/comment/d158053d_8134a84e?usp... : PS10, Line 4: register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "4" : register "gpu_dp_d_hotplug" = "4" Move under igd device
https://review.coreboot.org/c/coreboot/+/85772/comment/2be77e37_e4bf6d9d?usp... : PS10, Line 24: register "gen1_dec" = "0x000c0291" : register "gen2_dec" = "0x000c0241" : register "gen3_dec" = "0x000c0251" Move under lpc device (probably between subsystem and the superio)
https://review.coreboot.org/c/coreboot/+/85772/comment/2283ac31_80c3c270?usp... : PS10, Line 28: register "sata_interface_speed_support" = "0x3" : register "sata_port_map" = "0x3f" Move under sata1 device
https://review.coreboot.org/c/coreboot/+/85772/comment/2e0557fa_9d6f263c?usp... : PS10, Line 32: register "superspeed_capable_ports" = "0x0000000f" Move under xhci device
https://review.coreboot.org/c/coreboot/+/85772/comment/ac93cba4_62913ecb?usp... : PS10, Line 49: register "xhci_overcurrent_mapping" = "0x00000c03" : register "xhci_switchable_ports" = "0x0000000f" Move under xhci device
https://review.coreboot.org/c/coreboot/+/85772/comment/bcb49124_4fa49ea7?usp... : PS10, Line 57: device ref mei2 off end : device ref me_ide_r off end : device ref me_kt off end : device ref gbe off end Defaults to off in chipset devicetree, could be removed
https://review.coreboot.org/c/coreboot/+/85772/comment/f7e1a1cc_3df5327c?usp... : PS10, Line 71: device ref pcie_rp2 off end : device ref pcie_rp3 off end Defaults to off in chipset devicetree, could be removed
https://review.coreboot.org/c/coreboot/+/85772/comment/92b4e9b1_c4374f10?usp... : PS10, Line 91: device ref pci_bridge off end Defaults to off in chipset devicetree, could be removed.
https://review.coreboot.org/c/coreboot/+/85772/comment/57c79c23_f25f3567?usp... : PS10, Line 157: end Move to previous line
https://review.coreboot.org/c/coreboot/+/85772/comment/c80c32d7_a42fc228?usp... : PS10, Line 166: device ref sata2 off end : device ref thermal off end Defaults to off in chipset devicetree, could be removed
File src/mainboard/asrock/z77_extreme4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/85772/comment/e239c5ed_fe91a166?usp... : PS10, Line 5: #include <southbridge/intel/bd82x6x/pch.h> Doesn't seem to be used, remove.