[coreboot-gerrit] [S] Change in coreboot[main]: soc/amd/glinda: Assert on unsupported settings

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86498?usp=email )

Change subject: soc/amd/glinda: Assert on unsupported settings
......................................................................

soc/amd/glinda: Assert on unsupported settings

The FSP for glinda with version RXBCB0090C doesn't support ASPM L0s
and when a PCIe device is configured for L1 SS it never wakes and thus
is gone forever.

Assert when an unsupported configuration is used until the FSP has been
fixed.

Change-Id: If54542e17e6ac923b8d73bbb80712b9fdf07b44d
Signed-off-by: Patrick Rudolph 
---
M src/soc/amd/glinda/fsp_m_params.c
1 file changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/86498/1

diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c
index 1d297d4..92614ce 100644
--- a/src/soc/amd/glinda/fsp_m_params.c
+++ b/src/soc/amd/glinda/fsp_m_params.c
@@ -58,6 +58,16 @@

mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio,
    					&fsp_ddi, &num_ddi);
+
+	for (size_t i = 0; i < num_dxio; i++) {
+		// ASPM L0s isn't supported by FSP
+		assert (fsp_dxio[i].link_aspm != ASPM_L0s && fsp_dxio[i].link_aspm != ASPM_L0sL1);
+
+		// Device in L1 SS never wake...
+		assert (!fsp_dxio[i].link_aspm_L1_1);
+		assert (!fsp_dxio[i].link_aspm_L1_2);
+	}
+
    fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio);
    fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi);
 }